The second related application discloses a new form or type of integrated circuit, referred to as an adaptive computing engine (“ACE”), which is readily reconfigurable, in real time, and is capable of having corresponding, multiple modes of operation.
The ACE architecture, for adaptive or reconfigurable computing, includes a plurality of different or heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to adapt (configure and reconfigure) the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.
The ACE architecture utilizes a data flow model for processing. More particularly, input operand data will be processed to produce output data (without other intervention such as interrupt signals, instruction fetching, etc.), whenever the input data is available and an output port (register or buffer) is available for any resulting output data. Controlling the data flow processing to implement an algorithm, however, presents unusual difficulties, such as in the communication and control algorithms used in wideband CDMA (“WCDMA”) and cdma2000.
More particularly, many algorithms are not designed for processing using a data flow model such as that employed in the ACE architecture. Rather than being executed in a data flow-based system which executes when the data and output ports are available, many such algorithms are designed for implementation using systems having other, specific forms of processing control. For example, digital signal processor (“DSP”) implementations may provide control over processing using program instructions and interrupt signals over many clock cycles, while application specific integrated circuits (“ASICs”) may implement the algorithm directly in the fixed circuit layout, also for execution over many clock cycles.
This data flow model for processing, while invaluable for efficiency and other considerations, creates data flow control concerns which should be addressed in the adaptive computing architecture. These concerns, among others, include when processing of input data should begin for a given task, when processing of input data should end for the given task, and how these determinations should be made. In addition, the ACE architecture should provide for control over processing of multiple tasks, such as tasks (e.g., exception tasks) which may occur intermittently during performance of another task (e.g., a normal or regular task).
The ACE architecture should also provide for synchronization between and among the processing of multiple tasks occurring within an ACE device or system. For example, in WCDMA and cdma2000, searching tasks for selection of one or more multipaths should be synchronized with corresponding demodulation tasks by one or more rake fingers, such that control is provided over where in a data stream each rake finger task should commence demodulation.